{"id":9649971,"date":"2019-06-01T00:20:00","date_gmt":"2019-05-31T21:20:00","guid":{"rendered":"http:\/\/iee.it.teithe.gr\/course\/%cf%83%cf%87%ce%b5%ce%b4%ce%af%ce%b1%cf%83%ce%b7-%ce%b5%cf%80%ce%b1%ce%bd%ce%b1%cf%80%cf%81%ce%bf%cf%83%ce%b4%ce%b9%ce%bf%cf%81%ce%b9%ce%b6%cf%8c%ce%bc%ce%b5%ce%bd%cf%89%ce%bd-%cf%88%ce%b7%cf%86%ce%b9\/"},"modified":"2025-02-09T22:08:39","modified_gmt":"2025-02-09T19:08:39","slug":"1714","status":"publish","type":"course","link":"https:\/\/www.iee.ihu.gr\/en\/course\/1714\/","title":{"rendered":"Design of Reconfigurable Digital Systems (FPGAs)"},"content":{"rendered":"<p><span class=\"tlid-translation translation\" lang=\"en\">The structure of the course is shown below:<br \/>\nFPGA Structure and Function<br \/>\nIntroduction to the implementation of digital systems with FPGA<br \/>\nModeling &#8211; Introduction to VHDL Material Schematic Language<br \/>\nIntroduction to Verilog hardware description language<br \/>\nVHDL Language Entities and Architecture<br \/>\nWays to describe with VHDL: behavior, data flow, structural<br \/>\nData types, circuit data statement<br \/>\nCreation of subprograms, packages, libraries, layouts<br \/>\nTime Flow Handling &#8211; Sequential and Concurrent Suggestions<br \/>\nDescription of laboratory development system<br \/>\nUsing specialized software &#8211; Utilities<br \/>\nEmbedded systems<br \/>\nFPGA system design methodology<br \/>\nModern FPGA technology and architecture<br \/>\nVirtex and Spartan FPGAs as examples of modern redesigned architectures.<br \/>\nSynthesis, placement, routing in FPGAs<br \/>\nEmbedded processors (Xilinx Microblaze processor example)<br \/>\nMicroblaze Processor System on chip architecture<br \/>\nMatlab &#8211; Simulink &#8211; Xilinx System Generator &#8211; Xilinx ISE<\/span><\/p>","protected":false},"author":1,"template":"","meta":{"_acf_changed":false,"inline_featured_image":false,"footnotes":""},"class_list":["post-9649971","course","type-course","status-publish","hentry"],"acf":[],"aioseo_notices":[],"post-meta-fields":{"course-semester":["7"],"_course-semester":["field_5d132f2c14d55"],"course-id":["1714"],"_course-id":["field_5d132b9c78b6e"],"course-group":["\u0397\u039b\u0395\u03a3"],"_course-group":["field_5d14e905fe59a"],"course-type":["\u0395\u039e-\u0391\u0394"],"_course-type":["field_5d133c6ba1599"],"course-compulsory":["\u0395\u03a0"],"_course-compulsory":["field_5d146d39805a6"],"course-field":["\u0395\u03a5\u03a3"],"_course-field":["field_5d146e248f2b3"],"course-ects":["6"],"_course-ects":["field_5d13518794761"],"course-hours-theory":["2"],"_course-hours-theory":["field_5d13521894762"],"course-hours-lab":["2"],"_course-hours-lab":["field_5d1468d18a11f"],"_edit_lock":["1739127976:1"],"_edit_last":["1"],"course-school":["School of Engineering"],"_course-school":["field_5d132bf078b70"],"course-dept":["Department of Information and Electronic Engineering"],"_course-dept":["field_5d132c3a78b71"],"course-level":["1"],"_course-level":["field_5d132c5878b72"],"course-lang":["a:1:{i:0;s:2:\"el\";}"],"_course-lang":["field_5d133e246f04b"],"course-erasmus":["1"],"_course-erasmus":["field_5d133e8e6f04c"],"course-url":["https:\/\/www.iee.ihu.gr\/course\/1714\/"],"_course-url":["field_5d133f9b5c292"],"course-prerequisites":["a:2:{i:0;s:7:\"9649953\";i:1;s:7:\"9649938\";}"],"_course-prerequisites":["field_5d13405189c17"],"course-aim":["The purpose of the course is to understand the digital circuit design methodology in FPGA \/ VHDL \/ Schematic and Verilog languages \u200b\u200bon reconfigurable platforms as well as the general principles of their architecture.\r\nThe course will provide students with theoretical knowledge and practical laboratory experience in the design of embedded systems. The course emphasizes the design of hardware and software systems in FPGA (reconfigurable logic) devices. In the lab courses students will use FPGA systems and hardware and software design tools to design, implement and optimize Systems On Chip systems for an application.\r\nThe lesson has a task in which students working in groups are invited to implement an integrated system of their own choosing. The project includes a demo of the system in the classroom, presentation and report.\r\nUpon successful completion of the course the student will be able to:"],"_course-aim":["field_5d1353f985af8"],"course-goal-1":["Uses digital circuit design methodology with VHDL \/ Schematic language and FPGA programming"],"_course-goal-1":["field_5d13546e85af9"],"course-goal-2":["Uses digital circuit design methodology with Verilog language and FPGA programming"],"_course-goal-2":["field_5d1354f885afa"],"course-goal-3":["Understands the structure and functionality of a complex System On Chip"],"_course-goal-3":["field_5d13550085afb"],"course-goal-4":["Understands and uses reconfigurability"],"_course-goal-4":["field_5d13550e85afc"],"course-goal-5":["Gain new knowledge in hardware and software design for such a computer system."],"_course-goal-5":["field_5d13551485afd"],"course-goal-6":["Work and understand concepts such as hardware design, systems software, system on chips on a practical level."],"_course-goal-6":["field_5d13551b85afe"],"course-goal-7":[""],"_course-goal-7":["field_5d13552385aff"],"course-skills":["Search, analyze and synthesize data and information using the necessary technologies\r\nDecision making\r\nIndependent work\r\nTeamwork\r\nWorking in an international environment\r\nExercising criticism and self-criticism\r\nPromoting free, creative and inductive thinking"],"_course-skills":["field_5d1355c25aeb4"],"course-teaching-method":["Face to face theoretical teaching.\r\nLaboratory training."],"_course-teaching-method":["field_5d1383ec75a23"],"course-it-methods":["Power point presentations software.\r\nElectronic communication with students.\r\nUse of asynchronous education technology."],"_course-it-methods":["field_5d1384b975a24"],"course-activity-1":["Lectures"],"_course-activity-1":["field_5d1387d7cba43"],"course-activity-workload-1":["52"],"_course-activity-workload-1":["field_5d1388b2cba46"],"course-activity-2":["Writing and presenting compulsory work"],"_course-activity-2":["field_5d13886ccba44"],"course-activity-workload-2":["40"],"_course-activity-workload-2":["field_5d1388e9cba47"],"course-activity-3":["Individual study and analysis of literature"],"_course-activity-3":["field_5d138878cba45"],"course-activity-workload-3":["60"],"_course-activity-workload-3":["field_5d13890dcba49"],"course-activity-4":["Preparation for laboratory exercises and projects"],"_course-activity-4":["field_5d138947cba4b"],"course-activity-workload-4":["28"],"_course-activity-workload-4":["field_5d13891dcba4a"],"course-activity-5":[""],"_course-activity-5":["field_5d14ed2508982"],"course-activity-workload-5":[""],"_course-activity-workload-5":["field_5d14ed3708983"],"course-student-evaluation":["The grade of the course is derived from the final exam of the semester and from the work that the students are preparing and presenting. The course must be at least five (5).\r\nThe thesis deals with topics related to recent developments in the redesign of digital circuits and is presented by students in groups of two (usually) individuals. It is based on recent and reliable bibliography and includes a text description of approximately 2000 words and a presentation file with approximately 25 slides. The presentation of the work (20\u0384-30\u0384 duration) takes place during the teaching hours and attendance is compulsory for all students.\r\nAssessment criteria are accessible to students from the course web site."],"_course-student-evaluation":["field_5d1389cff8c01"],"course-eudoxus-bib":["P.J. Ashenden, Morgan Kaufmann, \"The Designer's Guide to VHDL, Vol. 3\", Elsevier"],"_course-eudoxus-bib":["field_5d138e0af441c"],"course-greek-bib":["Kang Sung - Mo (Steve), Leblebici Yusuf, \u0391\u03bd\u03ac\u03bb\u03c5\u03c3\u03b7 \u03ba\u03b1\u03b9 \u03c3\u03c7\u03b5\u03b4\u03af\u03b1\u03c3\u03b7 \u03c8\u03b7\u03c6\u03b9\u03b1\u03ba\u03ce\u03bd \u03bf\u03bb\u03bf\u03ba\u03bb\u03b7\u03c1\u03c9\u03bc\u03ad\u03bd\u03c9\u03bd \u03ba\u03c5\u03ba\u03bb\u03c9\u03bc\u03ac\u03c4\u03c9\u03bd CMOS, \u0395\u03ba\u03b4. \u03a4\u03b6\u03b9\u03cc\u03bb\u03b1.\r\nP.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, \u0391\u03bd\u03ac\u03bb\u03c5\u03c3\u03b7 \u03ba\u03b1\u03b9 \u03a3\u03c7\u03b5\u03b4\u03af\u03b1\u03c3\u03b7 \u0391\u03bd\u03b1\u03bb\u03bf\u03b3\u03b9\u03ba\u03ce\u03bd \u039f\u03bb\u03bf\u03ba\u03bb\u03b7\u03c1\u03c9\u03bc\u03ad\u03bd\u03c9\u03bd \u039a\u03c5\u03ba\u03bb\u03c9\u03bc\u03ac\u03c4\u03c9\u03bd, \u0395\u03ba\u03b4. \u039a\u03bb\u03b5\u03b9\u03b4\u03ac\u03c1\u03b9\u03b8\u03bc\u03bf\u03c2."],"_course-greek-bib":["field_5d138e3cf441d"],"course-intl-bib":["\"Embedded Computing, A VLIW Approach to Architecture, Compilers and Tools\" \r\nby Josh Fisher, Paolo Faraboschi, Cliff Young, Morgan Kaufmann Publishers\r\nDigital design: an embedded systems approach using VHDL"],"_course-intl-bib":["field_5d138e74f441e"],"course-rel-journals":["ACM Transactions on Reconfigurable Technology and Systems (TRESTS)\r\nInternational Journal of Reconfigurable Computing\r\nIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"_course-rel-journals":["field_5d138ec4f441f"],"course-teachers":[""],"_course-teachers":["field_5d3aa2923f803"],"_wp_old_slug":["%cf%83%cf%87%ce%b5%ce%b4%ce%af%ce%b1%cf%83%ce%b7-%ce%b5%cf%80%ce%b1%ce%bd%ce%b1%cf%80%cf%81%ce%bf%cf%83%ce%b4%ce%b9%ce%bf%cf%81%ce%b9%ce%b6%cf%8c%ce%bc%ce%b5%ce%bd%cf%89%ce%bd-%cf%88%ce%b7%cf%86%ce%b9"],"course-coordinator":["a:1:{i:0;s:7:\"9651008\";}"],"_course-coordinator":["field_5faa4466f1b87"],"_aioseo_title":[null],"_aioseo_description":[null],"_aioseo_keywords":["a:0:{}"],"_aioseo_og_title":[null],"_aioseo_og_description":[null],"_aioseo_og_article_section":[""],"_aioseo_og_article_tags":["a:0:{}"],"_aioseo_twitter_title":[null],"_aioseo_twitter_description":[null]},"_links":{"self":[{"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/course\/9649971","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/course"}],"about":[{"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/types\/course"}],"author":[{"embeddable":true,"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/users\/1"}],"version-history":[{"count":3,"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/course\/9649971\/revisions"}],"predecessor-version":[{"id":9673139,"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/course\/9649971\/revisions\/9673139"}],"wp:attachment":[{"href":"https:\/\/www.iee.ihu.gr\/en\/wp-json\/wp\/v2\/media?parent=9649971"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}